Do I wire up MS for dual wheel on a '99?
07-25-2006, 01:09 PM
#21
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Originally Posted by fluke
Ok, I understand how this would work if there was only 1 signal per 2 crank rotations since you could tell MS: "OK, when you receive the cmp signal reset because that's cylinders 1,4 TDC." As I understand it, MS has to know not only when the cylinders reach TDC but whether it's cylinders 1,4 or 2,3 so that it doesn't spark at BDC.
Originally Posted by fluke
I don't see how MS could do this with 2 rising voltage signals per crank rotation as is the case in the '99+ sensor, unless you set it to distinguish between the single and double pulses (but how?) Since the <'97 has 2 signals per 2 crank rotations (1 cam rotation) each signal will reset for cylinders 1,4 or 2,3 (I don't know which) w/ wasted spark.
Originally Posted by fluke
Basically, unless you can distinguish between the double pulse and the single pulse I don't think you can use the '99+ cmp.
Originally Posted by fluke
I would be interested in inverting the '99+ ckp signal and using that since there are twice as many signals per rotation and therefore double the precision. But, since it looks like I have to use the <'97 CAS for the cmp signal I might as well make it simple and use the ckp as well...
Jim
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07-25-2006, 03:03 PM
#22
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Even if we could convert the 2 pulses into 1 pulse, there are twice as many as can be used to isolate cylinders 1,4 from 2,3. I think you would need to take out either the lone pulse, and combine the 2 pulses or take out the 2 pulses. Holy ****, it's too complicated; I'm just going to use the older CAS I think. I'm sure it can be done w/ a cap/resistor network but I only had 1st year electronics (for engineers) and don't really know how to do anything w/ them.
Originally Posted by Reverant
Like I said you don't need to invert. Maybe we can collectively develop a small circuit using a cheapo microcontroller (ie Atmel AT90S1200) and feed the CMP signal to the microcontroller, which will "sanitize" the signal for us (convert the double pulse to single pulse). I'm scrap at analog electronics so I wouldn't know how to do this with plain-old resistors-capacitors-diodes-transistors.
Jim
Jim
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07-25-2006, 03:17 PM
#23
I have never looked at the trigger wheel in person but would it be possible to make a new one with the holes that are suitable for MS?
Other than that I could imagine a counter of some sort that only would pass on every second pulse (e.g. only the short one).
Isn't there any other signals from the crank or cam that can be used to create the signal we are looking for?
Other than that I could imagine a counter of some sort that only would pass on every second pulse (e.g. only the short one).
Isn't there any other signals from the crank or cam that can be used to create the signal we are looking for?
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07-26-2006, 11:27 AM
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No, per 2 crank rotations (1 full cycle) it sees 8 pulses (1 per 90 deg of crank) whereas the <97 sees 4 (1 per 180 deg of crank)
Originally Posted by kingofl337
So you are saying that the crank wheel on the 99+ has eight teeth instead of 4?
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07-28-2006, 07:44 AM
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Any thoughts on how to rectify the cmp signal?
BTW: I was wrong about the cmp signal, if you look at the plot that I posted there are two cmp signals per cycle (2 crank rotations) where one of them is a "double" pulse. So, if we could somehow merge the double pulse then we might be in business.
Strange though, it looks like if the pulses reset for 1-4 or 2-3 it would be out of phase by 90deg. Does MS have a setting for this? I mean we can't fire on the next ckp pulse after a cmp pulse when they're out of phase like this...
Edit: And it looks like they're resets for 2-3 , not 1-4, can MS be setup for this?
BTW: I was wrong about the cmp signal, if you look at the plot that I posted there are two cmp signals per cycle (2 crank rotations) where one of them is a "double" pulse. So, if we could somehow merge the double pulse then we might be in business.
Strange though, it looks like if the pulses reset for 1-4 or 2-3 it would be out of phase by 90deg. Does MS have a setting for this? I mean we can't fire on the next ckp pulse after a cmp pulse when they're out of phase like this...
Edit: And it looks like they're resets for 2-3 , not 1-4, can MS be setup for this?
Originally Posted by kingofl337
Not yet its my next project.
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07-28-2006, 09:09 AM
#32
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Originally Posted by fluke
Any thoughts on how to rectify the cmp signal?
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07-28-2006, 11:21 AM
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See, the problem is that I don't understand any of this stuff yet. Looking into that microcontroller thing totally confused me. What's "complex bool logic"? Are you talking about boolean gates? I've never worked w/ those in a practical sense. 
What might the circuit look like?
Things are so much simpler in mechanical engineering.
I started a post on miata.net:
http://forum.miata.net/vb/showthread...90#post1943890
What might the circuit look like?
Things are so much simpler in mechanical engineering.
Originally Posted by Reverant
Like I said, propably only with a microcontroller or with pretty complex bool logic (better off with an FPGA chip).
I started a post on miata.net:
http://forum.miata.net/vb/showthread...90#post1943890
Last edited by fluke; 07-28-2006 at 01:13 PM.
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07-29-2006, 05:23 PM
#35
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Originally Posted by kingofl337
I wonder if you could clean up that extra little spike with a CAP.
You propably could, if you knew that the CAS would be spinning constantly at X rpm. Since the engine speed varies from 200rpm (cranking) to 7000rpm (redline), finding the correct capacitance value is quite a trick!
Jim
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07-30-2006, 10:03 AM
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I don't know who's been following the tread at miata.net but we're making some headway w/ the flip flop idea.
I think that by using a SR flip flop we can rectify the cmp signal...
1- Wire the cmp to the "S" (signal) input
2- Wire the ckp to the "R" (reset) input
3- Output is "Q"
This way, the single cmp pulse sets the output to the high voltage; when the next ckp pulse comes along it sets the output low. Three more ckp pulses do nothing to the output signal since it's already in the low state. The first of the double pulses sets the output voltage high, the second is ignored because the output state is already high. The next ckp pulse sets the output voltage low, this is the 5th (total) ckp signal so far. Again, the next three ckp pulses are ignored because the output voltage is already low.
I don't think a cap would work very well because of the huge change in time between the two pulses at idle and 7500 RPM, and the proximity to the single pulse.
I think that by using a SR flip flop we can rectify the cmp signal...
1- Wire the cmp to the "S" (signal) input
2- Wire the ckp to the "R" (reset) input
3- Output is "Q"
This way, the single cmp pulse sets the output to the high voltage; when the next ckp pulse comes along it sets the output low. Three more ckp pulses do nothing to the output signal since it's already in the low state. The first of the double pulses sets the output voltage high, the second is ignored because the output state is already high. The next ckp pulse sets the output voltage low, this is the 5th (total) ckp signal so far. Again, the next three ckp pulses are ignored because the output voltage is already low.
I don't think a cap would work very well because of the huge change in time between the two pulses at idle and 7500 RPM, and the proximity to the single pulse.
Last edited by fluke; 07-30-2006 at 10:37 AM.
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07-30-2006, 04:01 PM
#37
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Originally Posted by fluke
I think that by using a SR flip flop we can rectify the cmp signal...
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07-30-2006, 07:12 PM
#38
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Dude, I barely know the theory. We need someone practical here to setup a circuit. For sure we need clock circuit, power circuit and latch (flip flop).
This could be a seriously cheap and elegant solution if it works.
Latches from digikey are cheap.
We could copy the megasquirt power supply and clock circuits.
This could be a seriously cheap and elegant solution if it works.
Latches from digikey are cheap.
We could copy the megasquirt power supply and clock circuits.
Originally Posted by Reverant
Give me a part number and a schematic and I can have the results by tomorrow.
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07-31-2006, 03:06 AM
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Ok I remembered a bit about SR latches from college so the circuit in the digital omain shouldn't be a problem. What remains is the voltage "drain" instead of spike issue. Ie the S and R inputs should be at the TTL level (0-2V for logical 0, 3.5V to 5V for logical 1).
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